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1.使用"加減計數(shù)"指令，可以遞增和遞減輸出CV的計數(shù)器值。
2. 當輸入CU的信號狀態(tài)從低電平（“0”）變?yōu)楦唠娖剑?ldquo;1”）時（即信號上升沿觸發(fā)），當前計數(shù)器值將加1并存儲在輸出CV中。當輸入CD的信號狀態(tài)從低電平（“0”）變?yōu)楦唠娖剑?ldquo;1”）時（即信號上升沿觸發(fā)），輸出CV的計數(shù)器值將減1。如果在一個程序周期內(nèi)，同時出現(xiàn)CU和CD的信號上升沿，輸出CV的當前計數(shù)器值將保持不變。
3. 計數(shù)器值可以不斷遞增，直到達到輸出CV所指定的數(shù)據(jù)類型的上限。一旦達到上限，即使出現(xiàn)信號上升沿，計數(shù)器值也不再遞增。達到指定數(shù)據(jù)類型的下限后，計數(shù)器值將不再遞減。
4. 當輸入LD的信號狀態(tài)變?yōu)楦唠娖剑?ldquo;1”）時，輸出CV的計數(shù)器值將設(shè)置為參數(shù)PV的值。只要輸入LD的信號狀態(tài)仍為高電平（“1”），輸入CU和CD的信號狀態(tài)就不會影響該指令的執(zhí)行。
5. 當輸入R的信號狀態(tài)變?yōu)楦唠娖剑?ldquo;1”）時，將計數(shù)器值重置為0。只要輸入R的信號狀態(tài)仍為高電平（“1”），輸入CU、CD和LD的信號狀態(tài)的變化將不會影響"加減計數(shù)"指令。
6. 如果當前計數(shù)器值大于或等于參數(shù)PV的值，則將輸出QU的信號狀態(tài)置為高電平（“1”）。在其他情況下，輸出QU的信號狀態(tài)為低電平。
7. 如果當前計數(shù)器值小于或等于0，則將輸出QD的信號狀態(tài)置為高電平（“1”）。在其他情況下，輸出QD的信號狀態(tài)為低電平（“0”）。
1. Use the "add subtract count" command to increase and decrease the counter value of the output CV.
When the signal state of the input CU changes from low level ("0") to high level ("1") (i.e. the rising edge of the signal is triggered), the current counter value will be incremented by 1 and stored in the output CV. When the signal state of the input CD changes from low level ("0") to high level ("1") (i.e. the rising edge of the signal is triggered), the counter value of the output CV will decrease by 1. If both CU and CD signal rising edges occur within one program cycle, the current counter value of the output CV will remain unchanged.
3. The counter value can continuously increase until it reaches the upper limit of the data type specified by the output CV. Once the upper limit is reached, even if there is a rising edge of the signal, the counter value will no longer increase. After reaching the lower limit of the specified data type, the counter value will no longer decrease.
When the signal state of the input LD changes to high level ("1"), the counter value of the output CV will be set to the value of the parameter PV. As long as the signal status of the input LD remains high ("1"), the signal status of the input CU and CD will not affect the execution of the instruction.
When the signal state of input R changes to high level ("1"), reset the counter value to 0. As long as the signal state of the input R remains high ("1"), changes in the signal state of the input CU, CD, and LD will not affect the "add subtract count" instruction.
If the current counter value is greater than or equal to the value of parameter PV, set the signal state of output QU to high level ("1"). In other cases, the signal state of the output QU is low.
If the current counter value is less than or equal to 0, set the signal status of the output QD to high level ("1"). In other cases, the signal state of the output QD is low ("0").
